4QD-TEC Electronics Circuits Reference Archive
In case you have not read it, Part 1 of Timer Circuits
This page describes in detail two similar circuits and how they can be built to plug into the Adaptable relay module to give it the following timer functions:
The DOE and the period timer are actually the same circuit but different outputs are used.
The logic ICs
The top circuit uses NAND gates. The logic of a gate such as these can be described by a 'truth table' as below:
An interesting fact about NAND and NOR gates: if you take the NAND gate logic and invert every item, it becomes a NOR gate. By invert, I mean write 1 where there was a 0 and write 0 where there was a 1. So the gates have identical function, but one is an 'invert' of the other. If you were doing this with transistors, you could change from one gate to the other by swapping PNP transistors for NPN, and turning the result upside down! The actual circuit configurations would be identical.
If this 'interesting thought' seems odd, then consider the following two statements:
It should be obvious from this that the two statements are the same but with 'high' and 'low' transposed. So it should come as no surprise that the DOD timer uses the same circuit a the DOE but with a 4001 NOR gate. However, instead of pulling the NAND's inputs low, the NOR's must be pulled high so link A is made rather than link B.
DOE (Delay on Energise)
The top circuit, DOE (Delay on Energise) uses a CMOS quad NAND gate (4011). Pin D is the input (pin numbers mate up with the relay driver's personality connector). The input is decoupled with a 100K/100n (CR=10mS) to give noise immunity, necessary in most industrial environments!
When the input (on N1 pins 1 and 2) goes high, N1's output (pin3) goes low so N2's output must go high.
This takes N3's input (pins 8 and 9) high so its output (pin 10) goes low.
Notice the three 'link pads' A, B and C. C may be made if remote control of the timer is required: terminal E then connects to the timing pot. In the DOE timer, link B is made, so that C2 now starts to charge through the preset VR1. During the charge period, N4 pin 11 is high and N3 pin 8/9 is falling slowly to zero volts.
Before the input changed from low to high, N4 had pin 13 low and pin 12 high. After the transition, pin 13 is high and pin 12 is low. In both cases, pin 11 will be high high and the output not energised.
When the capacitor has charged enough, N3's inputs pass the gates operating threshold. At this threshold, the output changes.
N4 now has two highs on its inputs so its output goes low, so its output goes low and turns on the transistor output stage. The time period has elapsed and the output (pin C) goes high after the delay. A high input is delayed by a timed period, before the output goes high. This is the correct function of a positive logic 'Delay on energise' timer.
During the delay period, N3's output is low. So during this period, Tr1 will be turned on and output C will be high. This is the 'period' output: the output goes high on a positive input transition, stays high for a timed period, then goes low.
I said above that before and after the input change from low to high, pin 11 of N4 was high. This is not quite true. There is a propagation delay around N2/N3 so there is a slight delay between N4 pin 13 going high and pin 12 going low. During this slight delay, there is a momentary spike output on pin C. However, this is generally too fast for the relay drive circuit to react, so it can be ignored. However, if an oscilloscope is used to examine the circuit, this 'glitch' can trigger the oscilloscope sweep, so it can actually be useful!
Inputs and Outputs
In industrial machines, interference and voltage spikes are common. Circuits for use in such an environment must be protected against these and against wiring faults and other misadventure.
Unprotected CMOS logic is not very good for industrial use - its inputs are easily blown by static or by voltage transients - or even by doing silly things to the output. So the input to this timer is decoupled by 100K resistors and the outputs are pull-up transistors, but with a limited current drive ability. See the article Current Sources and Mirrors for more information on current sources. This output drive circuit will stand most types of wiring mistakes.
DOD (Delay on De-energise)
The more astute amongst you will have noticed that the DOD circuit (lower of the two) is very similar to the DOE one. You may re-read the above description, replacing low by high, up by down, and vice versa etc.
In all circuits, the designer must consider the situation when power is applied to the circuit: many a time failure to consider this has caused a re-design! At power up, C2 is discharged. The inputs to N1 will be low, N2's output will go high. But this is a delay on de-energise circuit... We don't want to start with the input (N1 pin 1/2) low but with it high. Whatever circuit is driving this is most likely to start in the wrong state, then there's going to be a small delay while C1 charges up. All of this is going tp give a false output pulse!
This is the reason for Tr3 and its circuit. Call it a 'power-on reset' if you will. Before applying power, C4 is discharged. At power-on, it must charge. it does so and current flows out of Tr3's base, turning Tr3 on. This clamps pins 8/9 of N3 high during the power up, so there is no false output pulse and the timer can start in the correct state.
The circuit board
The diagrams above show the circuit board viewed 'through' the board, from the component side. In the second drawing, the components have ben removed. You can see the link pads A, B and C, but mirrored as we are looking through the board.
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First published: 3rd of January, 2002